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-- F4 port
-- Fabf 03-2016

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity f4_port is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
D7 : inout STD_LOGIC;
WR : in STD_LOGIC;
RD : in STD_LOGIC;
IORQ : in STD_LOGIC;
RESET : in STD_LOGIC
);
end f4_port;

architecture Behavioral of f4_port is

signal f4_status : std_logic :='1';

BEGIN

process(A,D7,WR,RD,IORQ,RESET)
variable f4_init : std_logic ;
BEGIN
if (RESET = '0') then
f4_init := '1';
elsif A(7 downto 0) = "11110100" AND IORQ = '0' AND WR = '0' then
f4_init := D7;
else
f4_status <= f4_init;
END IF;

end process;

D7 <= f4_status when A(7 downto 0) = "11110100" AND IORQ = '0' AND RD = '0' else 'Z';

end Behavioral;